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a AD8110 / ad8111 260 mhz, 16 8 buffered video crosspoint switches features 16 8 high-speed nonblocking switch arrays AD8110: g = +1 ad8111: g = +2 serial or parallel switch array control serial data out allows daisy chaining of multiple crosspoints to create larger switch arrays pin-compatible with ad8108/ad8109 8 8 switch arrays for a 16 16 array see ad8116 complete solution buffered inputs eight output amplifiers, AD8110 (g = +1), ad8111 (g = +2) drives 150 v loads excellent video performance 60 mhz 0.1 db gain flatness 0.02% differential gain error (r l = 150 v) 0.028 differential phase error (r l = 150 v) excellent ac performance 260 mhz C3 db bandwidth 500 v/ms slew rate low power of 50 ma low all hostile crosstalk of C78 db @ 5 mhz output disable allows direct connection of multiple device outputs reset pin allows disabling of all outputs (connected through a capacitor to ground provides power- on reset capability) excellent esd rating: exceeds 4000 v human body model 80-lead lqfp package (12 mm 12 mm) applications routing of high-speed signals including: composite video (ntsc, pal, s, secam) component video (yuv, rgb) compressed video (mpeg, wavelet) 3-level digital video (hdb3) functional block diagram AD8110/ad8111 switch matrix output buffer g = +1, g = +2 40 40 128 40-bit shift register with 5-bit parallel loading parallel latch decode 8 5:16 decoders 8 clk data in update ce reset 16 inputs a0 data out 8 outputs set individual or reset all outputs to "off" a1 a2 ser/par d0 d1 d2 d3 enable/disable d4 product description the AD8110 and ad8111 are high-speed 16 8 video cross- point switch matrices. they offer a C3 db signal band width greater than 260 mhz, and channel switch times of less than 25 ns with 1% settling. with C78 db of crosstalk and C97 db isolation (@ 5 mhz), the AD8110/ad8111 are useful in many high-speed applications. the differential gain and differential phase of better than 0.02% and 0.02 respectively, along with 0.1 db flatness out to 60 mhz, make the AD8110/ad8111 ideal for video signal switching. the AD8110 and ad8111 include eight independent output buffers that can be placed into a high impedance state for paral- leling crosspoint outputs so that off channels do not load the output bus. the AD8110 has a gain of +1, while the ad 8111 offers a gain of +2. they operate on voltage supplies of 5 v while consuming only 50 ma of idle current. the channel switching is performed via a serial digital control (which can accommodate daisy chaining of several devices) or via a parallel control, allowing updating of an individual output without repro- gramming the entire array. the AD8110/ad8111 is packaged in an 80-lead lqfp package and is available over the extended industrial temperature range of C40 c to +85 c. rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2016 analog devices, inc. all rights reserved. technical support www.analog.com
C2C AD8110/ad8111Cspecifications (v s = 5 v, t a = +25 c, r l = 1 k unless otherwise noted.) AD8110/ad8111 parameter conditions min typ max unit reference dynamic performance C3 db bandwidth 200 mv p-p, r l = 150 300/190 390/260 mhz tpc 1, 7 2 v p-p, r l = 150 150 mhz tpc 1, 7 propagation delay 2 v p-p, r l = 150 5ns slew rate 2 v step, r l = 150 500 v/ s settling time 0.1%, 2 v step, r l = 150 40 ns tpc 6, 12 gain flatness 0.05 db, 200 mv p-p, r l = 150 60/40 mhz tpc 1, 7 0.05 db, 2 v p-p, r l = 150 65/40 mhz tpc 1, 7 0.1 db, 200 mv p-p, r l = 150 80/57 mhz tpc 1, 7 0.1 db, 2 v p-p, r l = 150 70/57 mhz tpc 1, 7 noise/distortion performance differential gain error 0.01 % 0.02 % differential phase error 0.01 degrees 0.02 degrees crosstalk, all hostile o 78/o 85 db tpc 2, 8 o 7 / o 8 db tpc 2, 8 off isolation, input-output o 9 / o db tpc 17, 23 input voltage noise ntsc or pal, r l = 1 k ntsc or pal, r l =150 ntsc or pal, r l = 1 k ntsc or pal, r l = 150 f = 5 mhz f = 10 mhz f = mhz, r l =150 , one channel 0.01 mhz to 50 mhz 15 nv/ hz tpc 14, 20 dc performance gain error r l = 1 k 0.04/0.1 0.07/0.5 % r l = 150 0.15/0.25 % gain matching no load, channel-channel 0.02/1.0 % r l = 1 k , channel-channel 0.09/1.0 % gain temperature coefficient 0.5/8 ppm/ c output characteristics output impedance dc, enabled 0.2 18, 24 disabled 10/0.001 m 15, 21 output disable capacitance disabled 2 pf output leakage current disabled, AD8110 only 1/na a output voltage range no load 2.5 3v output current 20 40 ma short circuit current 65 ma input characteristics input offset voltage worst case (all configurations) 5 20 mv 29, 35 temperature coefficient 12 v/ c 30, 36 input voltage range 2.5/ 1.25 3/ 1.5 v input capacitance any switch configuration 2.5 pf input resistance 1 10 m input bias current per output selected 2 5 a switching characteristics enable on time 60 ns switching time, 2 v step 50% update to 1% settling 25 ns switching transient (glitch) measured at output 20/30 mv p-p 16, 22 power supplies supply current avcc, outputs enabled, no load 38 ma avcc, outputs disabled 15 ma avee, outputs enabled, no load 38 ma avee, outputs disabled 15 ma dvcc 11 ma supply voltage range 4.5 to 5.5 v psrr f = 100 khz 75/78 db 13, 19 f = 1 mhz C55/C58 db operating temperature range temperature range operating (still air) C40 to +85 c ja operating (still air) 48 c/w specifications subject to change without notice. 3&7#
3&7# AD8110/ad8111 ?3? timing characteristics (serial) l i i i i ii i ii ii i ii i i ii ii i i iiii i i i i i
3&7# AD8110/ad8111 ?4? timing characteristics (parallel) l i i i i i i i i i i i ii i i iii i i i i i
3&7# AD8110/ad8111 ?5? caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD8110/ad8111 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.0 v internal power dissipation 2 AD8110/ad8111 80-lead plastic lqfp (st) . . . . . 2.6 w input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v s output short circuit duration . . . . . . . . . . . . . . . . . . . . . observe power derating curves storage temperature range . . . . . . . . . . . . ?65 c to +125 c lead temperature range (soldering 10 sec) . . . . . . . . 300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 specification is for device in free air (t a = 25 c): 80-lead plastic lqfp (st): ja = 48 c/w. maximum power dissipation the maximum power that can be safely dissipated by the AD8110/ad8111 is limited by the associated rise in junction temperature. the maximum safe junction tem perature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150 c. temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. exceeding a junction temperature of 175 c for an extended period can result in device failure. while the AD8110/ad8111 is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (150 c) is not exceeded under all conditions. to ensure proper operation, it is necessary to observe the maximum power derating curves shown in figure 3. ambient temperature ? c 5.0 maximum power dissipation ? watts 4.0 0 ?50 80 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 3.0 2.0 1.0 t j = 150 c 90 figure 3. maximum power dissipation vs. temperature
3&7# AD8110/ad8111 ?6? table iii. operat i ser ce update c data dataut reset par i ii f f f f ff f
3&7# AD8110/ad8111 ?7? pin function descriptions p i i i i i ii iii ii iiii ii ii i i ii ii iiii iiii ii ii iii iii i i i i i i i i i i reset t t e tt
AD8110/ad8111 in oniuation 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 56 57 58 59 54 55 52 53 50 51 60 45 46 47 48 43 44 42 49 41 5 4 3 2 7 6 9 8 1 11 10 16 15 14 13 18 17 20 19 12 pin 1 identifier AD8110/ad8111 40 39 38 37 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 36 dgnd dvcc in07 agnd in06 agnd in05 agnd in04 agnd in03 agnd in02 agnd in01 agnd in00 dvcc dgnd rese t agnd07 avee06/07 out06 agnd06 avcc05/06 out05 agnd05 avee04/05 out04 agnd04 avcc03/04 out03 agnd03 avee02/03 out02 agnd02 avcc01/02 out01 agnd01 ce data out clk data in update ser/par a0 a1 a2 d0 d1 d2 d3 d4 agnd avee avcc avcc00 agnd00 out00 in08 agnd in09 agnd in10 agnd in11 agnd in12 agnd in13 agnd in14 agnd in15 agnd avee avcc avcc07 out07 avee00/01 16 8 80-lead lqfp (12mm 12mm) top view (not to scale) 0.5mm lead pitch 3&7# ?
3&7# ?9? typical performance characteristics?AD8110/ad8111 frequency ? hz gain ? db ?2 1 0 ?1 ?3 100k 1m 1g 10m 100m flatness ? db 0.2 0.1 0 ?0.1 ?0.2 ?0.3 gain flatness 2 3 0.3 4 5 200mv p-p 2v p-p r l = 150 tpc 1. AD8110 frequency response frequency ? mhz crosstalk ? db ?30 ?40 ?100 0.3 1 200 10 100 ?50 ?60 ?70 ?80 ?90 adjacent all hostile r l = 1k tpc 2. AD8110 crosstalk vs. frequency frequency ? hz distortion ? db 100k 1m 100m 10m ?100 ?40 ?50 ?60 ?70 ?80 ?90 2nd harmonic 3rd harmonic r l = 150 v out = 2v p-p tpc 3. AD8110 distortion vs. frequency 50 25 0 25 50 25ns/div 25mv/div r l = 150 tpc 4. AD8110 step response, 100 mv step 1 0.5 0 0.5 1 25ns/div 0.5v/div r l = 150 tpc 5. AD8110 step response, 2 v step 2v step r l = 150 0 10 20304050607080 10ns/div 0.1%/div tpc 6. AD8110 settling time
3&7# AD8110/ad8111 ?10? frequency ? hz gain ? db ?2 1 0 ?1 ?3 100k 1m 1g 10m 100m flatness ? db 0.4 0.2 0 ?0.2 ?0.4 2 3 0.6 gain flatness ?0.6 0.8 200mv p-p 2v p-p ?0.8 4 5 tpc 7. ad8111 frequency response frequency ? mhz crosstalk ? db ?20 ?30 ?90 0.3 1 200 10 100 ?40 ?50 ?60 ?70 ?80 ?100 ?110 r l = 1k adjacent all hostile tpc 8. ad8111 crosstalk vs. frequency frequency hz distortion db 30 40 100 100k 1m 100m 10m 50 60 70 80 90 2nd harmonic 3rd harmonic r l = 150 v out = 2v p-p tpc 9. ad8111 distortion vs. frequency 50 25 0 25 50 25ns/div 25mv/div tpc 10. ad8111 step response, 100 mv step 1 0.5 0 0.5 1 25ns/div 500mv/div tpc 11. ad8111 step response, 2 v step 2v step rto r l = 150 0 10 20304050607080 10ns/div 0.1%/div tpc 12. ad8111 settling time
3&7# AD8110/ad8111 ?11? frequency hz power supply rejection db 30 40 10k 100k 10m 1m 50 60 70 80 90 r l = 150 tpc 13. AD8110 psrr vs. frequency frequency hz 100 56.3 10 1k 10m 100k 31.6 17. 8 10 5.63 3.16 100 10k 1m nv/ hz tpc 14. AD8110 voltage noise vs. frequency frequency mhz output impedance 1m 0.1 1 500 10 100k 10k 1k 100 100 tpc 15. AD8110 output impedance, disabled update input typical video out (rto) 5 4 3 2 1 0 10 ?10 0 50ns/div 10mv/div 1v/div switching between two inputs tpc 16. AD8110 switching transient (glitch) frequency ? hz off isolation ? db 100k 1m 500m 10m 100m v in = 2v p-p r l = 150 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 tpc 17. AD8110 off isolation, input-output 10,000 1000 100 10 1 0.1 frequency ? hz output impedance ? 100k 1m 500m 10m 100m tpc 18. AD8110 output impedance, enabled
3&7# AD8110/ad8111 ?12? frequency ? hz power supply rejection ? db rti 10k 100k 1m 10m ?30 ?40 ?50 ?60 ?70 ?80 r l = 150 tpc 19. ad8111 psrr vs. frequency frequency hz 100 56.3 10 1k 10m 100k 31.6 17.8 10 5.63 3.16 100 10k 1m nv/ hz tpc 20. ad8111 voltage noise vs. frequency frequency mhz output impedance 100k 0.1 1 500 10 10k 1k 100 10 100 tpc 21. ad8111 output impedance, disabled 1v/div update input typical video out (rto) 10mv/div 5 4 3 2 1 0 10 0 ?10 50ns/div switching between two inputs tpc 22. ad8111 switching transient (glitch) frequency ? hz off isolation ? db 100k 1m 500m 10m 100m ?60 ?80 ?100 ?120 ?130 ?110 ?90 ?70 ?50 v out = 2v p-p r l = 150 ?40 ` tpc 23. ad8111 off isolation, input-output frequency hz output impedance 1k 100k 1m 500m 10m 100 10 1 0.1 100m tpc 24. ad8111 output impedance, enabled
3&7# AD8110/ad8111 ?13? input impedance ? 1m 100k 10k 1k 100 10m 30k 100k 1m 10m 100m 500m frequency ? hz tpc 25. AD8110 input impedance vs. frequency frequency ? hz gain ? db 14 12 ?4 0.1m 1m 10m 100m 1g 10 8 0 6 4 2 ?2 18pf = 7.7db 12pf = 4.5db 3g v in = 200mv p-p r l = 150 tpc 26. AD8110 f requency response vs. capacitive load frequency ? hz flatness ? db 0.7 0.6 ?0.2 0.1m 1m 10m 100m 1g 0.5 0.4 0 0.3 0.2 0.1 ?0.1 v in = 200mv p-p r l = 150 c l = 18pf c l = 12pf 3g tpc 27. AD8110 flatness vs. capacitive load v out update input 1 at +1v input 0 at ?1v 1 0 ?1 5 0 50ns/div 2v/div 1v/div tpc 28. AD8110 switching time offset voltage ? volts frequency 260 60 ?0.020 ?0.010 0.000 0.010 240 180 160 120 80 220 200 140 100 40 20 0 0.020 tpc 29. AD8110 offset voltage distribution temperature ? c v os ? mv 2.0 ?2.0 ?60 ?40 100 ?20 0 20 40 60 80 1.5 0 ?0.5 ?1.0 ?1.5 1.0 0.5 tpc 30. AD8110 offset voltage vs. temperature (normalized at 25 c)
3&7# AD8110/ad8111 ?14? frequency ? hz input impedance ? 30k 1m 500m 10m 100m 1m 100k 10k 1k 100 100k 10m tpc 31. ad8111 input impedance vs. frequency gain ? db 12 10 ?6 8 6 ?2 4 2 0 ?4 frequency ? hz 0.1m 1m 10m 100m 1g 3g 18pf 12pf tpc 32. ad8111 f requency response vs. capacitive load gain ? db 0.7 0.6 ?0.1 0.5 0.4 0 0.3 0.2 0.1 ?0.2 ?0.3 frequency ? hz 0.1m 1m 10m 100m 1g 3g 12pf 18pf v in = 100mv r l = 150 tpc 33. ad8111 flatness vs. capacitive load v out update input 1 at +1v input 0 at ?1v 1 0 ?1 5 0 50ns/div 2v/div 1v/div tpc 34. ad8111 switching time offset voltage ? volts frequency 120 480 360 320 240 160 440 400 280 200 80 40 0 ?0.020 0.020 ?0.010 0.000 0.010 tpc 35. ad8111 offset voltage distribution (rti) temperature ? c v os ? mv 2.0 ?2.0 ?60 ?40 100 ?20 0 20 40 60 80 1.5 0 ?0.5 ?1.0 ?1.5 1.0 0.5 tpc 36. ad8111 offset voltage drift vs. temperature (normalized at 25 c)
3&7# AD8110/ad8111 ?15? theory of operation the AD8110 (g = +1) and ad8111 (g = +2) share a common core architecture consisting of an array of 128 transconductance (gm) input stages organized as eight 16:1 multiplexers with a common, 16-line analog input bus. each multiplexer is basically a folded-cascode high-speed voltage feedback amplifier with 16 input stages. the input stages are npn differential pairs whose differential current outputs are combined at the output stage, which contains the high impedance node, compensation and a complementary emitter follower output buffer. in the AD8110, the output of each multiplexer is fed directly back to the inverting inputs of its 16 gm stages. in the ad8111, the feedback network is a voltage divider consisting of two equal resistors. this switched-gm architecture results in a low power crosspoint switch that is able to directly drive a back terminated video load (150 ) with low distortion (differential gain and differential phase errors are better than 0.02% and 0.02 , respectively). this design also achieves high input resistance and low input ca paci- tance without the signal degradation and power dissipation of additional input buffers. however, the small input bias current at any input will increase almost linearly with the number of out- puts programmed to that input. the output disable feature of these crosspoints allows larger switch matrices to be built simply by busing together the outputs of multiple 16 8 ics. however, while the disabled output im ped- ance of the AD8110 is very high (10 m ), that of the ad8111 is limited by the resistive feedback network (which has a nominal total resistance of 1 k ) that appears in parallel with the disabled output. if the outputs of multiple ad8111s are connected th rough separate back termination resistors, the loading due to these finite output impedances will lower the effective back termination impedance of the overall matrix. this problem is eliminated if the outputs of multiple ad8111s are connected directly and share a single back termination resistor for each output of the overall matrix. this configuration increases the capacitive loading of the disabled ad8111 on the output of the enabled ad8111. applications the AD8110/ad8111 have two options for changing the programming of the crosspoint matrix. in the first option, a serial word of 40 bits can be provided that will update the entire matrix each time. the second option allows for changing a single output?s programming via a parallel interface. the serial option requires fewer signals, but requires more time (clock cycles) for changing the programming, while the parallel programming tech- nique re quires m ore signals, but can change a single output at a time and re quires fewer clock cycles to complete programming. ser i i iiii ii iii i ii i ii iiii iii iiiiiii ii i iiiiii iii iii ii iii iii iiii ii iii iii iiiiiii iiiiii iiiii iiiii ii i i i iii iii i ii i ii iiiiii iiii iiii iii iiiii i iiii iii iiiii iiii iiiiii ii iiiiiii i i i ii iiii iii iiiiiiii i ii i iii ii i iiii i
3&7# AD8110/ad8111 ?16? this will ensure that the programming matrix is always in a known state. from then on, parallel programming can be used to modify a single output or more at a time. in a similar fashion, if both ce and update are taken low after initial power-up, the random power-up data in the shift register will be programmed into the matrix. therefore, in order to prevent the crosspoint from being programmed into an unknown state do not apply low logic levels to both ce update p t e pa update ce tc t aatdd td d dd a ct update t c update update t peeet adad t eet eet adadt p t ce update t update t eet ddd a eet eet t t aeect t tad tad tad adt a dad ceataecptaa tadad ad adad t t adad tpc a t
3&7# AD8110/ad8111 ?17? the basic concept in constructing larger crosspoint arrays is to connect inputs in parallel in a horizontal direction and to ?wire-or? the outputs together in the vertical direction. the meaning of horizontal and vertical can best be understood by looking at a diagram. figure 6 illustrates this concept for a 32 8 crosspoint array. AD8110 or ad8111 16 16 r term in 00?15 AD8110 or ad8111 16 16 r term in 16?31 8 8 figure 6. a 32 8 crosspoint array using two AD8110s or two ad8111s the inputs are each uniquely assigned to each of the 32 inputs of the two devices and terminated appropriately. the outputs are wire-ored together in pairs. the output from only one of a wired or pair should be enabled at any given time. the device programming software must be properly written to cause this to happen. at some point, the number of outputs that are wire-ored becomes too great to maintain system performance. this will vary ac cording to which system specifications are most important. it will also depend on whether the matrix consists of AD8110s or ad8111s. the output disabled impedance of the AD8110 is much higher than that of the ad8111, so its disabled parasitics will have a smaller effect on the one output that is enabled. for e xample, a 128 8 crosspoint can be created with eight AD8110/ad8111s. this design will have 128 separate inputs and have the corresponding outputs of each device wire-ored together in groups of eight. using additional crosspoint devices in the design can lower the number of outputs that must be wire-ored together. figure 7 shows a block diagram of a system using eight AD8110s and two ad8111s to create a nonblocking, gain -of-two, 128 8 crosspoint that restricts the wire-oring at the output to only four outputs. these devices are the AD8110, which has a higher disabled output impedance than the ad8111. additionally, by using the lower four outputs from each of the two rank 2 ad8111s, a blocking 128 16 crosspoint array can be realized. there are, however, some drawbacks to this tech- nique. the offset voltages of the various cascaded devices will accumulate and the bandwidth limitations of the devices will compound. in addition, the extra devices will consume more current and take up more board space. once again, the overall system design specifications will determine how to make the various tradeoffs. 16 r term in 00?15 4 4 in 16?31 in 32?47 in 48?63 in 64?79 in 80?95 in 96?111 in 112?127 4 4 4 4 rank 2 16:8 nonblocking (16:16 blocking) rank 1 (8 x AD8110) 128:16 16 r term 4 4 16 r term 4 4 16 r term 4 4 16 r term 4 4 16 r term 4 4 16 r term 4 4 16 r term 4 4 ad8111 AD8110 AD8110 AD8110 AD8110 AD8110 AD8110 AD8110 AD8110 4 1k 4 1k 4 1k 4 1k ad8111 out 00 ? 07 nonblocking additional 8 outputs (subject to blocking) figure 7. a gain-of-two 128 8 nonblocking crosspoint array (128 16 blocking)
3&7# AD8110/ad8111 ?18? mult i i iiii iiiii i iii iii iiii ii iii ii iiiiii iiiii ii ii iiii iii iiii i iiiii iiiiii ii iiiiii iiiii iiii iiiii iiiiii iiii iiiii iiii iiii iii ii ii iiiii iiiii iii i iii iiiiii iiiii iiii iiiii iii i iiiii iiiiii iiii iii i ii iiii iii ii i iii i iii iiii iiiiiii iiii iiii i iiii iiiii iiii i iiiiii i ii iiii iiii iiiii i iiiiii iii iiiiii iii i iiiii iiii iiiii iii ii iiii ii i ii ii i ii ii i iii ii iiiiiiiii iiii iiiiiii iiii ii iiii ii ii iii i iiiii iiii ii iii i iiii iii ii iiiiii iii
3&7# AD8110/ad8111 ?19? measur i iii iiii i iii xt asel s atest s 20 10 log / lol l loolglll logl olooooo goglooo olglllloglo olooolool ogooog oooolgl ooogolgo ololoooo llgolo1 8 matrix of the AD8110/ad8111, we can examine the number of crosstalk terms that can be considered for a single channel, say in00 input. in00 is programmed to connect to one of the AD8110/ad 8111 outputs where the measurement can be made. we can first measure the crosstalk terms associated with driving a test signal into each of the other 15 inputs one at a time. we can then measure the crosstalk terms associated with driving a parallel test signal into all 15 other inputs taken two at a time in all possible combinations; and then three at a time, etc., until, finally, there is only one way to drive a test signal into all 15 other inputs. each of these cases is legitimately different from the others and might yield a unique value depending on the resolution of the measurement system, but it is hardly practical to measure all these terms and then to specify them. in addition, this describes the crosstalk matrix for just one input channel. a similar crosstalk matrix can be proposed for every other input. in addition, if the possible combinations and permutations for connecting inputs to the other (not used for measurement) outputs are taken into consideration, the numbers rather quickly grow to astronomical proportions. if a larger crosspoint array of multiple AD8110/ad8111s is constructed, the numbers grow larger still. obviously, some subset of all these cases must be selected to be used as a guide for a practical measure of crosstalk. one common method is to measure ?all hostile? crosstalk. sus term means that the crosstalk to the selected channel is measured, while all other system channels are driven in parallel. in general, this will yield the worst crosstalk number, but this is not always the case due to the vector nature of the crosstalk signal. other useful crosstalk measurements are those created by one nearest neighbor or by the two nearest neighbors on either side. these crosstalk measurements will generally be higher than those of more distant channels, so they can serve as a worst-case measure for any other one-channel or two-channel crosstalk measurements. input and output crosstalk the flexible programming capability of the AD8110/ad8111 can be used to diagnose whether crosstalk is occurring more on the input side or the output side. some examples are illustrative. a given input channel (in07 in the middle for this example) can be programmed to drive out03. the input to in07 is just terminated to ground (via 50 or 75 ) and no signal is applied. all the other inputs are driven in parallel with the same test signal (practically provided by a distribution amplifier), with all other outputs except out03 disabled. since grounded in07 is programmed to drive out03, there should be no signal present. any signal that is present can be attributed to the other 15 hostile input signals, because no other outputs are driven. (they are all disabled.) thus, this method measures the all-hostile input contribution to crosstalk into in07. of course, the method can be used for other input channels and combinations of hostile inputs. for output crosstalk measurement, a single input channel (in00 for example) is driven and all outputs other than a given output (in03 in the middle) are programmed to connect to in00. out03 is programmed to connect to in15 (far away from in00), which is terminated to ground. thus out03 should not have a signal present since it is listening to a quiet input. any signal measured at the out03 can be attributed to the output crosstalk of the other seven hostile outputs. again, this method can be modified to measure other channels and other crosspoint matrix combinations. effect of impedances on crosstalk the input side crosstalk can be influenced by the output impedance of the sources that drive the inputs. the lower the impedance of the drive source, the lower the magnitude of the crosstalk. the dominant crosstalk mechanism on the input side is capacitive coupling. the high impedance inputs do not have significant current flow to create magnetically induced crosstalk. however, significant current can flow through the input termi- nation resistors and the loops that drive them. thus, the pc board on the input side can contribute to magnetically coupled crosstalk. from a circuit standpoint, the input crosstalk mechanism looks like a capacitor coupling to a resistive load. for low frequencies the magnitude of the crosstalk will be given by: xt r c s sm 20 10 log o l gll lol ooool glog olgologo oo lolggl loo oolg lglolog110/111 lllgg 10 oloolllg ologoll olloo oo110/111
3&7# AD8110/ad8111 ?20? from a circuit standpoint, this output crosstalk mechanism looks like a transformer with a mutual inductance between the windings that drives a load resistor. for low frequencies, the magnitude of the crosstalk is given by: xt mxy s r l 20 10 log / loo oo looo olgl log l loggooo gllllg o oolol go lllgoglgglog lg ggo110/111gol oloo ologgollool loogoloo goolglo loollolo ol ooogogo loggooologloo olooologlo ooogooloo lloggoolgl ololool gool001 ologolgo ologoo olooooo llologgo00 og0ol gloogoo og glolllloogol oglllol logololo logool lolooolo oolollo glooo ooglollo ooloogo g
AD8110/ad8111 rev. b ?21? outline dimensions compliant to jedec standards ms-026-bdd 051706-a 0.15 0.05 1.45 1.40 1.35 0.20 0.09 0.08 coplanarity view a rotated 90 ccw seating plane 7 3.5 0 top view (pins down) 1 21 41 40 60 61 80 20 0.50 bsc lead pitch 0.27 0.22 0.17 1.60 max 0.75 0.60 0.45 view a pin 1 14.20 14.00 sq 13.80 12.20 12.00 sq 11.80 figure 8. 80-lead low profile quad flat package [lqfp] (st-80-1) dimensions shown in millimeters d d odel 1 temerature ange package descrition package tion d8110st 0 to 8 80-lead low profile quad flat package [lqfp] st-80-1 d8111st 0 to 8 80-lead low profile quad flat package [lqfp] st-80-1 1 os-omliant part. s st /15rev. a to rev. b e to ot a ote ete oto ttt ete................................................................... 2 e to ae o ot eto ......................................... 1 eete vto bo eto e reee eet ...................................................................................... 20 eete e ............................................................................... 21 ove te eo e e revo to .............................................................................................. 21 te te eo ........................................................ 21 e to e e ........................................................... 21 eete e 10 e 11 ................................................... 22 eete e 12 e 1 ................................................... 2 eete e 1 oto te vto bo o eto e 15 .................................................................... 2 eete veoot o te ot t e eto e 1 ........................................................................................... 25 2/02rev. 0 to rev. a e to .................................................. ve oet ae to te eo ................................... 2 201 ao eve . a t eeve. e etee te e te oet o te eetve oe. 0100 /16(b)

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